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What is Set up and hold time?
How would you solve set-up time issues?
Why do set up time issues occur in a circuit? Theoretical questions based on Setup time were asked to solve.
How does setup time vary with respect to the PVT?
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What does "7nm" in 7 nm technology represent? How would you increase the buffer strength? Theoretical question based on cache and miss rate and virtual memory was asked to solve.
What is cross talk? How to prevent it?
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Numerical questions based on setup and hold time were asked
Which bulb will glow brighter- series or parallel? Draw the circuit for dividing 8-bit numbers by 5. What are rectifiers? How do Bridge wave rectifiers differ from Full-wave rectifiers? Explain using a diagram.
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Write C code for identifying repeated numbers in a given sequence using minimum complexity.
Draw XOR gate using NAND gate.
Draw FSM for divisible by 2 and divisible by 3 numbers.
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What is Leakage power? What is Short circuit power? Setup and hold violations NMOS and PMOS working
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Tell me as many ways as possible to design a gated clock. Tell me when and why we need clock gating.

Tell me the sources of leakage in CMOS system.

Draw a layout for a NAND gate
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how to solve setup violation? What the solution would impact on the other part of the design? how to deal with the SI issue? Clearly know about the calculation of setup time, or min clock period What is OCV on timing check๏ผŸhow to calculate? What is the CPPR?
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